Synthesis Report synthesis: version Radiant (64-bit) 1.0.1.350.6 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2018 Lattice Semiconductor Corporation, All rights reserved. Mon Nov 19 22:19:18 2018 Command Line: C:\lscc\radiant\1.0\ispfpga\bin\nt64\synthesis.exe -f SerialTest_impl_1_lattice.synproj -gui -msgset W:/projects/Ice40SerialTest/promote.xml Synthesis options: The -a option is iCE40UP. The -t option is SG48. The -sp option is High-Performance_1.2V. The -p option is iCE40UP5K. ########################################################## ### Lattice Family : iCE40UP ### Device : iCE40UP5K ### Package : SG48 ### Speed : High-Performance_1.2V INFO - synthesis: User-Selected Strategy Settings Optimization goal = Area Top-level module name = top. Target frequency = 1.000000 MHz. Maximum fanout = 1000. Timing path count = 3 RWCheckOnRam = 0 BRAM utilization = 100.000000 % DSP usage = true DSP utilization = 100.000000 % fsm_encoding_style = auto resolve_mixed_drivers = 0 fix_gated_clocks = 1 Mux style = auto (Default) Use Carry Chain = true carry_chain_length = 0 Loop Limit = 1950. Use IO Insertion = TRUE Use IO Reg = AUTO Resource Sharing = TRUE Propagate Constants = TRUE Remove Duplicate Registers = TRUE Output HDL file name = SerialTest_impl_1.vm. ROM style = auto RAM style = auto The -comp option is FALSE. The -syn option is FALSE. -sdc option: SDC file input is W:/projects/Ice40SerialTest/source/impl1.ldc. -path C:/lscc/radiant/1.0/ispfpga/ice40tp/data (searchpath added) -path W:/projects/Ice40SerialTest (searchpath added) -path W:/projects/Ice40SerialTest/impl_1 (searchpath added) Mixed language design Verilog design file = C:/lscc/radiant/1.0/ip/pmi/pmi.v VHDL library = pmi VHDL design file = C:/lscc/radiant/1.0/ip/pmi/pmi.vhd VHDL library = work VHDL design file = W:/projects/Ice40SerialTest/source/rs232_sender.vhd VHDL library = work VHDL design file = W:/projects/Ice40SerialTest/source/top.vhd VHDL library = work VHDL design file = W:/projects/Ice40SerialTest/source/rs232_receiver.vhd The -r option is OFF. [ Remove LOC Properties is OFF. ] Compile design. Compile Design Begin Analyzing Verilog file c:/lscc/radiant/1.0/ip/pmi/pmi.v. VERI-1482 INFO - synthesis: c:/lscc/radiant/1.0/ip/pmi/pmi.v(1): analyzing included file c:/lscc/radiant/1.0/ip/pmi/pmi_add.v. VERI-1328 INFO - synthesis: c:/lscc/radiant/1.0/ip/pmi/pmi_add.v(50): analyzing included file c:/lscc/radiant/1.0/ip/pmi/../common/adder/rtl/lscc_adder.v. VERI-1328 INFO - synthesis: c:/lscc/radiant/1.0/ip/pmi/pmi.v(2): analyzing included file c:/lscc/radiant/1.0/ip/pmi/pmi_complex_mult.v. VERI-1328 INFO - synthesis: c:/lscc/radiant/1.0/ip/pmi/pmi_complex_mult.v(52): analyzing included file c:/lscc/radiant/1.0/ip/pmi/../common/complex_mult/rtl/lscc_complex_mult.v. VERI-1328 INFO - synthesis: c:/lscc/radiant/1.0/ip/pmi/pmi.v(3): analyzing included file c:/lscc/radiant/1.0/ip/pmi/pmi_dsp.v. VERI-1328 INFO - synthesis: c:/lscc/radiant/1.0/ip/pmi/pmi.v(4): analyzing included file c:/lscc/radiant/1.0/ip/pmi/pmi_mac.v. VERI-1328 INFO - synthesis: c:/lscc/radiant/1.0/ip/pmi/pmi_mac.v(52): analyzing included file c:/lscc/radiant/1.0/ip/pmi/../common/mult_accumulate/rtl/lscc_mult_accumulate.v. VERI-1328 INFO - synthesis: c:/lscc/radiant/1.0/ip/pmi/pmi.v(5): analyzing included file c:/lscc/radiant/1.0/ip/pmi/pmi_multaddsub.v. VERI-1328 INFO - synthesis: c:/lscc/radiant/1.0/ip/pmi/pmi_multaddsub.v(52): analyzing included file c:/lscc/radiant/1.0/ip/pmi/../common/mult_add_sub/rtl/lscc_mult_add_sub.v. VERI-1328 INFO - synthesis: c:/lscc/radiant/1.0/ip/pmi/pmi.v(6): analyzing included file c:/lscc/radiant/1.0/ip/pmi/pmi_mult.v. VERI-1328 INFO - synthesis: c:/lscc/radiant/1.0/ip/pmi/pmi_mult.v(51): analyzing included file c:/lscc/radiant/1.0/ip/pmi/../common/multiplier/rtl/lscc_multiplier.v. VERI-1328 INFO - synthesis: c:/lscc/radiant/1.0/ip/pmi/pmi.v(7): analyzing included file c:/lscc/radiant/1.0/ip/pmi/pmi_ram_dp.v. VERI-1328 INFO - synthesis: c:/lscc/radiant/1.0/ip/pmi/pmi_ram_dp.v(47): analyzing included file c:/lscc/radiant/1.0/ip/pmi/../common/ram_dp/rtl/lscc_ram_dp.v. VERI-1328 INFO - synthesis: c:/lscc/radiant/1.0/ip/pmi/pmi.v(8): analyzing included file c:/lscc/radiant/1.0/ip/pmi/pmi_ram_dq.v. VERI-1328 INFO - synthesis: c:/lscc/radiant/1.0/ip/pmi/pmi_ram_dq.v(45): analyzing included file c:/lscc/radiant/1.0/ip/pmi/../common/ram_dq/rtl/lscc_ram_dq.v. VERI-1328 INFO - synthesis: c:/lscc/radiant/1.0/ip/pmi/pmi.v(9): analyzing included file c:/lscc/radiant/1.0/ip/pmi/pmi_sub.v. VERI-1328 INFO - synthesis: c:/lscc/radiant/1.0/ip/pmi/pmi_sub.v(50): analyzing included file c:/lscc/radiant/1.0/ip/pmi/../common/subtractor/rtl/lscc_subtractor.v. VERI-1328 Analyzing VHDL file c:/lscc/radiant/1.0/ip/pmi/pmi.vhd. VHDL-1481 INFO - synthesis: c:/lscc/radiant/1.0/ip/pmi/pmi.vhd(4): analyzing package components. VHDL-1014 unit top is not yet analyzed. VHDL-1485 Analyzing VHDL file w:/projects/ice40serialtest/source/rs232_sender.vhd. VHDL-1481 INFO - synthesis: w:/projects/ice40serialtest/source/rs232_sender.vhd(12): analyzing entity rs232_sender. VHDL-1012 INFO - synthesis: w:/projects/ice40serialtest/source/rs232_sender.vhd(25): analyzing architecture rtl. VHDL-1010 unit top is not yet analyzed. VHDL-1485 Analyzing VHDL file w:/projects/ice40serialtest/source/rs232_receiver.vhd. VHDL-1481 INFO - synthesis: w:/projects/ice40serialtest/source/rs232_receiver.vhd(11): analyzing entity rs232_receiver. VHDL-1012 INFO - synthesis: w:/projects/ice40serialtest/source/rs232_receiver.vhd(21): analyzing architecture rtl. VHDL-1010 unit top is not yet analyzed. VHDL-1485 Analyzing VHDL file w:/projects/ice40serialtest/source/top.vhd. VHDL-1481 INFO - synthesis: w:/projects/ice40serialtest/source/top.vhd(8): analyzing entity top. VHDL-1012 INFO - synthesis: w:/projects/ice40serialtest/source/top.vhd(18): analyzing architecture rtl. VHDL-1010 unit top is not yet analyzed. VHDL-1485 INFO - synthesis: The default VHDL library search path is now "W:/projects/Ice40SerialTest/impl_1". VHDL-1504 Top module language type = VHDL. unit top is not yet analyzed. VHDL-1485 w:/projects/ice40serialtest/source/top.vhd(8): executing top(rtl) WARNING - synthesis: w:/projects/ice40serialtest/source/top.vhd(29): using initial value 'U' for led_latch_blue since it is never assigned. VHDL-1303 INFO - synthesis: w:/projects/ice40serialtest/source/top.vhd(66): going to verilog side to elaborate module SP256K. VHDL-1399 INFO - synthesis: w:/projects/ice40serialtest/source/top.vhd(66): back to VHDL to continue elaboration. VHDL-1400 INFO - synthesis: w:/projects/ice40serialtest/source/top.vhd(78): going to verilog side to elaborate module RGB. VHDL-1399 INFO - synthesis: w:/projects/ice40serialtest/source/top.vhd(78): back to VHDL to continue elaboration. VHDL-1400 WARNING - synthesis: w:/projects/ice40serialtest/source/top.vhd(16): replacing existing netlist top(rtl). VHDL-1205 Top module name (VHDL, mixed language): top Loading device for application lse from file 'itpa08.nph' in environment: C:/lscc/radiant/1.0/ispfpga. ### Number of Logic Cells: 5280 ### Number of RAM Blocks: 30 ### Number of DSP Blocks: 8 ### Number of PLLs: 1 ### Number of IO Pins: 56 ########################################################## INFO - synthesis: Extracted state machine for register '\receiver/state' with one-hot encoding State machine has 4 reachable states with original encodings of: 00 01 10 11 original encoding -> new encoding (one-hot encoding) 00 -> 0001 01 -> 0010 10 -> 0100 11 -> 1000 WARNING - synthesis: Cell RGB already has the black_box_pad_pin attribute on RGB2. WARNING - synthesis: Cell RGB already has the black_box_pad_pin attribute on RGB1. WARNING - synthesis: Cell RGB already has the black_box_pad_pin attribute on RGB0. WARNING - synthesis: Skipping pad insertion on led_blue due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on led_green due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on led_red due to black_box_pad_pin attribute. Starting design annotation.... Starting full timing analysis... Starting design annotation.... Starting full timing analysis... Starting design annotation.... Starting full timing analysis... Starting design annotation.... Starting full timing analysis... Starting design annotation.... Starting full timing analysis... Area Report ################### Begin Area Report (top)###################### Number of register bits => 123 of 5280 (2 % ) CCU2 => 28 FD1P3XZ => 123 IB => 2 IOL_B => 2 LUT4 => 144 OB => 1 OB_RGB => 3 RGB_CORE => 1 VFB_B => 1 ################### End Area Report ################## Number of odd-length carry chains : 3 Number of even-length carry chains : 1 Clock Report ################### Begin Clock Report ###################### Clock Nets Number of Clocks: 1 Net : clk_c, loads : 0 Clock Enable Nets Number of Clock Enables: 15 Top 10 highest fanout Clock Enables: Net : n1131, loads : 39 Net : n1526, loads : 15 Net : n940, loads : 8 Net : sender/n1568, loads : 7 Net : receiver/n1477, loads : 7 Net : sender/n1506, loads : 7 Net : ram_maskwe[1], loads : 3 Net : sender/n1572, loads : 3 Net : ram_maskwe[3], loads : 3 Net : receiver/n1507, loads : 3 Highest fanout non-clock nets Top 10 highest fanout non-clock nets: Net : n1131, loads : 40 Net : high_byte, loads : 32 Net : n1700, loads : 23 Net : receiver/n755, loads : 20 Net : sender/state[1], loads : 19 Net : n938, loads : 18 Net : n1526, loads : 15 Net : n1679, loads : 14 Net : receiver/n770, loads : 14 Net : download_done, loads : 12 ################### End Clock Report ################## Peak Memory Usage: 145.219 MB -------------------------------------------------------------- Total CPU time for LSE flow : 3.594 secs Total REAL time for LSE flow : 4.000 secs --------------------------------------------------------------